Neuro-fuzzy architecture for CMOS implementation

In this paper, a nonconventional structure for a “fuzzy” controller is proposed. It does not require signal division, and it produces control surfaces similar to classical fuzzy controllers. The structure combines fuzzification, MIN operators, normalization, and weighted sum blocks. The fuzzy architecture is implemented as a VLSI chip using 2m n-well technology. A new fuzzification circuit, which requires only one differential pair per membership function is proposed. Eight equally spaced membership functions are used in the VLSI implementation. Simple voltage MIN circuits are used for rule selection. A modified Takagi–Sugeno approach with normalization and weighted sum is used in the defuzzification circuit. Weights in the defuzzifier are digitally programmable with 6-bits resolution.